1. Field of the Invention
The invention is directed to the field of signal translation between electronic circuits. More specifically, the invention is directed to the translation of information signals between electronic circuits which operate under different power supplies.
2. Description of Related Art
Modern computer systems typically include a variety of discrete electronic circuits. Although some effort is made to comply with established standards, circumstances often arise in which electronic circuits intended to be used together operate using different power supplies, often having different voltage ranges.
A common example of this is found when electronic circuits which are compatible with standard transistor-transistor-logic (TTL) interface with electronic circuitry which uses complementary metal oxide semiconductor (CMOS) devices. TTL devices often operate using a power supply rated at 3.3 volts, and contain logic levels (i.e., Boolean logic states representing "0" and "1") that require a signal level to be above a logical threshold (also known as a "trip point") of 1.4 volts to represent a logical "1" or a signal level below the trip point to represent a logical "0". CMOS devices, on the other hand, often operate using a power supply rated at 5.0 volts and require a signal level above a trip point of 2.5 volts to represent a logical "1" or a signal level below the trip point to represent a logical "0".
A similar problem exists when two core circuits operate under different power supplies on the same chip. For example, a single-chip graphics accelerator may include a basic logic section that operates under a power supply nominally rated at 1.8 volts, and a dynamic random access memory (DRAM) core section that operates under a different power supply nominally rated at 2.5 volts.
The problem that arises when different circuits operating with different power supplies interface with each other is that the threshold point (i.e., "trip point") in which a given signal is to be determined as being in one logical state or the other differs depending on the operating voltage of the power supply used. A TTL signal level of, for example, 2.0 volts is sufficient to trigger a logical "1", in a TTL receiving device. The same signal level, however, if received by a CMOS device would be detected as a logical "0," because the signal level would be below the 2.5 volt trip point of the CMOS device, thus creating an intolerable error in transmission between the TTL and CMOS devices.
Known attempts have been made to overcome this problem. Input buffers, for example, have been added to CMOS devices as an interface to receive input data signals from a TTL device and translate the input TTL signals into compatible CMOS output signals. Such an input buffer is able to differentiate between a received high and low TTL input signal by comparing the TTL input to a predetermined threshold value (i.e., trip point). The input signal is considered a high input if it has a voltage level greater than the trip point, and considered a low input if the voltage level is less than the trip point. The high/low states determined from this comparison can then be used to output signals which transition in a signal range which is compatible with downstream CMOS devices.
The predetermined threshold value or "trip point" is typically set by circuit designers to fall approximately midway between the expected high voltage levels (e.g., above 2.0 volts) and low voltage levels (e.g., below 0.8 volts) of the external circuitry (e.g., TTL) transmitting the input signals, as shown for example in U.S. Pat. No. 4,937,476. Such input buffers, however, are not able to take into account inherent variations in the trip points of different transmitting devices due to manufacturing tolerances and the like. For example, a typical power supply for a TTL device is nominally rated at 3.3 volts, but, in practice, may generate voltages anywhere from 2.8 volts to 3.7 volts during its operation and still be considered a rated 3.3 volt power supply. Any variation in the power supply level of the transmitting device will require a proportional change in the trip point used by the input buffer to properly translate the input signals.
Some input buffers, as described in U.S. Pat. No. 4,306,801, for example, although successful in translating signal levels from devices operating under different power supplies, suffer from propagation delay skew. This skew problem is exhibited when an input signal having a high-to-low (falling edge). transition is delayed through the input buffer much longer than that for an input signal having a low-to-high (rising edge) transition. The skew is attributed to the mobility difference between P-channel and N-channel semiconductor material that makes P-channel transistors inherently slower than N-channel transistors by a factor of 1.5 to 3.0. The complementary use of P-channel and N-channel transistors in these known input buffers can create a propagation delay skew.
The skew is also attributed to the fact that the trip point of the receiving circuit is closer to either the high or the low voltage state of the transmitting circuit. Where the high voltage state is closer to the trip point, for example, as shown in FIG. 4a, the falling edge transition time will be shorter than the rising edge transition time, thereby resulting in the skew problem.